LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY NOT1 IS
   PORT( 
      a : IN     STD_LOGIC;
      y : OUT    STD_LOGIC
   );
END NOT1 ;


ARCHITECTURE v OF NOT1 IS
BEGIN
  
  
  y <= NOT a;
  
END ARCHITECTURE v;

